Lagos, Nigeria
VHDL,Verilog,Systemverilog,Xilinx ISE,Vivado, Altera Quartus, Vivado H
Local Time - 05:00 PM
About Me
Years experience in RTL Design & Verification
10 year's experience in digital system design using VHDL and Verilog for FPGA's and CPLD's both for Xilinx and Altera Chips.
I also have 10 years experience in working with Xilinx Ise from version 6.2 to 14.7 and Altera Quarus 2 for VHDL, Verilog, System Verilog and ip in addition to experience in Vivado design tool, and HLS and digital design using zynq7000
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