About Me
Detail oriented VLSI Engineer with hands on
experience in RTL design and functional
verification using Verilog, System Verilog, and
UVM. Skilled in AXI, APB, AHB, and SPI
protocols, with strong knowledge of digital
electronics and scripting in Perl. Proficient in
industry tools like Questa SIM and EDA
Playground. Eager to contribute to cutting edge
semiconductor design and verification projects
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$12/hr
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